Xilinx Releases ISE Design Suite v13.4

Xilinx rolled out version 13.4 of their ISE Design Suite. ISE Design Suite 13.4 features public access to the MicroBlaze Micro Controller System (MCS), new RX Margin Analysis and debug capabilities for the 28nm 7 Series FPGAs and partial reconfiguration support for the Artix-7 family and Virtex-7 XT devices. ISE Design Suite v13.4 is available now for all ISE Editions. List prices start at $2,995 for the Logic Edition.

Xilinx ISE Design Suite v13.4 Highlights

MicroBlaze MCS
MicroBlaze Micro Controller System is new to the Xilinx LogiCORE IP core offering. It is included in all ISE Design Suite Editions, ISE WebPACK and is compatible with AutoESL high-level synthesis tool v2011.4. MicroBlaze MCS simplifies microcontroller-based designs and provides a turnkey microcontroller solution to Xilinx customers. It includes the MicroBlaze processor, local memory for program and data storage, as well as tightly coupled GPIO, timers, interrupt controllers and other standard peripherals. MCS is supported across a broad range of Xilinx FPGA families, and is pre-configured for easy deployment by hardware developers.

RX Margin Analysis Tool
ChipScope Pro now includes a new RX margin analysis tool, which helps engineers optimize signal quality and lower the bit error ratio (BER) on designs. The RX Margin Analysis tool uses 2-dimensional statistical Eye Scan algorithms to interactively characterize and optimize channel quality in real time, or during post-run processing.

PlanAhead Design and Analysis Tool
The PlanAhead tool is a comprehensive development environment for design creation, analysis, planning and implementation. It accelerates time to production with a unique integrated front-to-back environment that includes design analysis at each phase of the design cycle — RTL development, IP integration, verification, synthesis and place and route. The end result is rapid convergence on power consumption, resource utilization and performance with fewer time-consuming design iterations. Up front design analysis and design preservation flows that ensure timing from run to run are critical for customers targeting the new 7 series devices.

4th Generation Partial Reconfiguration
The PlanAhead tool offers partial reconfiguration support for Artix-7 and Virtex-7 XT FPGAs. Partial reconfiguration dynamically modifies logic blocks while the remaining logic operates without interruption. This means designers can use Artix-7 and Virtex-7 XT devices to build flexible systems that are able to swap functions and perform remote updates while operational. Partial reconfiguration also helps engineers to reduce costs and design size by taking advantage of time-multiplexing that ultimately leads to reduced board space and minimizes bitstream storage because smaller, or fewer, devices can be utilized. Smaller and fewer devices can also lead to reductions in system power, while swapping out power hungry tasks can minimize the FPGA’s dynamic power consumption.

Extended Support for 7 Series FPGAs
The latest version of ISE Design Suite provides public access for the Artix-7 and Virtex-7 XT FPGA families. This helps engineers in closing their designs, intelligent clock gating to reduce power, team design flows and fifth-generation partial reconfiguration technology now offered for Artix-7 FPGAs and Virtex-7 XT FPGAs. The Artix-7 FPGA offers the lowest power and lowest cost for high-volume markets. Virtex-7 XT FPGA devices feature the highest processing bandwidth with high performance transceivers, digital signal processing (DSP) and BRAM.

More info: Xilinx ISE Design Suite 13