Aldec, Inc. will offer support for Open Verification Methodology (OVM) 2.0, which is an open, language-interoperable verification methodology, co-developed by Cadence Design Systems, Inc. (NASDAQ: CDNS). The OVM-based release of the Aldec mixed-language HDL simulator will provide the OVM community additional choices and further reinforce the value of a widely supported open-source methodology. Aldec plans to integrate OVM 2.0 into its common-kernel, mixed-language, HDL simulator on the Windows® and Linux® 32/64 platforms. A preliminary release of the Aldec HDL Simulator Riviera-PRO[tm], supporting OVM 2.0, is scheduled for delivery in Q1 2009.
SystemVerilog users of Aldec tools will benefit from the OVM’s multi-language support of Transaction-Level Modeling (TLM), previously available only for SystemC. All foundation-level utilities, standard TLM interfaces and built-in debug support for TLM connections will enable Aldec users to build advanced object-oriented, coverage-driven verification environments in SystemVerilog. The Aldec simulation suite will support both the OVM 2.0 class library and methodology, helping engineers develop reusable, interoperable verification IP and create hierarchical environments that facilitate “plug-and-play” reusable verification.