Aldec, Inc. launched Riviera-PRO 2007.10 mixed-language design simulation environment. The latest release offers expanded SystemVerilog (Verification) construct support and improved performance of VHDL, Verilog, and mixed RTL simulation. Riviera-PRO 2007.10 supports VHDL, Verilog, SystemVerilog, and SystemC designs. Riviera-PRO also supports multi-million gate HDL designs.
Riviera-PRO 2007.10 now supports the SystemVerilog constructs for classes and strings. These constructs are typically used in verification functions as specified by Accellera SystemVerilog 3.1a / IEEE Std 1800-2005. In addition, VHDL RTL simulation performance is 30% faster and Verilog RTL simulation performance is up to 60% faster on large designs as compared to the previous release.
Riviera-PRO 2007.10 is available today and is sold directly from Aldec and its authorized world-wide distributors. Riviera-PRO is available in three new configurations LV, LVT and LVT-SV, all licenses are floating and support UNIX, Windows® and Linux 32/64.