Lattice PCI Express Root Complex Lite IP Core

Lattice Semiconductor introduced their PCI Express Root Complex (RC) Lite solution. Lattice PCI Express RC Lite is based on the LatticeECP3 and LatticeECP2M FPGA families. The programmable FPGA platform enables designers to implement the specific bridge function that matches the interface available on their particular host CPU. Designers can also implement multiple bridges or different configurations of bridges in a single FPGA. The PCI Express RC Lite IP core provides a x1 or x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in the PCI express protocol stack. The PCI Express Root Complex IP core is available now for a list price of $1,500 for the x1 IP core and $3,000 for the x4 IP core.

Lattice Semiconductor PCI Express Root Complex (RC) Lite IP Core

Lattice Semiconductor PCI Express RC Lite Features

  • 125 MHz user interface
    • x4 supports a 64-bit data path
    • x1 supports a 16-bit data path
  • In transmit, user creates TLPs without ECRC, LCRC, or sequence number
  • In receive, user receives valid TLPs without ECRC, LCRC, or sequence number
  • Credit interface for transmit and receive for PH, PD, NPH, NPD, CPLH, CPLD credit types
  • Higher layer control of LTSSM via ports
  • Transmit and Receive Flow control
  • Malformed and poisoned TLP detection
  • Optional ECRC generation/checking
  • INTx message TLP decoding and interrupt signaling to user
  • Error message TLP decoding and signaling to user
  • 128, 256, 512, 1k, 2k or 4k bytes maximum payload size
  • Data link control and management state machine
  • Flow control initialization
  • Ack/Nak DLLP generation/termination
  • LCRC generation/checking
  • Sequence number appending/checking/removing
  • Retry buffer and management
  • Receiver buffer
  • 2.5 Gbps CML electrical interface
  • PCI Express 1.1 electrical compliance
  • Many options for signal integrity including differential output voltage, transmit pre-emphasis and receiver equalization
  • Serialization and de-serialization
  • 8b10b symbol encoding/decoding
  • Link state machine for symbol alignment
  • Clock tolerance compensation supports +/- 300 ppm
  • Framing and application of symbols to lanes
  • Data scrambling and de-scrambling
  • Lane-to-lane de-skew
  • Link Training and Status State Machine (LTSSM)
    • Electrical idle generation
    • Receiver detection
    • TS1/TS2 generation/detection
    • Lane polarity inversion
    • Link width negotiation
    • Higher layer control to jump to defined states

More information: Lattice Semiconductor