Pentek Cobal Model 71662 Xilinx Virtex-6 FPGA Board

Pentek introduced the Cobal Model 71662 Xilinx Virtex-6 FPGA board. A variety of FPGA sizes are available for the Pentek 71662 module. Supported FPGAs include the LX240T, LX365T, SX315T, or SX475T devices. The 71662 features four transformer isolated input channels; Texas Instruments ADS5485 16-bit, 200 MHz ADC; built-in digital down converters (DDCs); input bandwidth from 300 kHz to 700 MHz; and four 512 MB DDR3 SDRAM memory banks. The Pentek 71662 XMC module is priced at $12,750 (USD). The board is also available in PCIe, VPX and cPCI formats, and conduction-cooled versions.

Pentek Cobal Model 71662 Xilinx Virtex-6 FPGA XMC board

Cobal Model 71662 FPGA Module Features

    Pentek Cobal Model 71662 Software Radio FPGA Module

  • Complete radar and software radio interface solution
  • Supports Xilinx Virtex-6 LXT and SXT FPGAs
  • LVDS connections to the Virtex-6 FPGA for custom I/O
  • Four 200 MHz 16-bit A/Ds
  • Four multiband DDCs
  • Sample clock synchronization to an external system reference
  • LVPECL clock/sync bus for multi-module synchronization
  • PCI Express (Gen. 1 and 2) interface up to x8
  • User-configurable serial gigabit interfaces
  • Input bandwidth from 300 kHz to 700 MHz
  • Suitable for direct connection to IF or RF ports of communications, unmanned autonomous vehicle (UAV) and radar systems
  • Four transformer-isolated input channels — each with a TI ADS5485 ADC
  • Input multiplexer supports four Acquisition IP modules factory-installed in the Xilinx Virtex-6 FPGA
  • Each IP module can receive data from any of the four ADCs, or from a test signal generator
  • Four 512 MB DDR3 SDRAM memory banks, one for each IP module
  • Buffers data in a FIFO mode or store data in a transient capture mode
  • DMA engines stream data at up to 1600 MB/second through the PCIe interface to off-board storage or additional processing
  • DMA engines automatically construct meta-data packets that contain information like channel ID, a sample-accurate time stamp and data length
  • 8-channel digital downconverter bank in each of the four Acquisition IP modules
  • Each DDC bank has its own decimation setting from 16 to 8192
  • Decimation FIR filter within each bank accepts a unique set of 18-bit user-supplied coefficients for custom channel shaping
  • Each of the eight DDC channels within a bank can have its own 32-bit tuning-frequency setting and delivers a complex output stream consisting of 24-bit I and 24-bit Q samples

More info: Pentek