Altera Quartus II Software 7.2

Altera Corporation (NASDAQ: ALTR) introduced version 7.2 of their Quartus® II software. With version 7.2, designers can expect their Stratix® III FPGAs compile-time advantage to grow to three times that of competing high-end 65-nm FPGAs. Quartus II software version 7.2 includes productivity and performance-focused enhancements that enable designers to achieve faster compile times and meet performance requirements. A Quartus II software user working with a multiprocessor computer will experience, on average, a 20 percent reduction in compile times over single-processor computers. In addition, enhanced place-and-route algorithms enable Stratix III customers to meet their high-performance requirements and offer a two speed grade advantage versus competitors.

Both the Subscription Edition and free Web Edition of Quartus II software version 7.2 are now available for download. The Subscription Edition is also available in DVD format by request. Altera’s software subscription program simplifies obtaining Altera® design software by consolidating software products and maintenance charges into one annual subscription payment. Subscribers receive Quartus II software, the ModelSim®-Altera edition and a full license to the IP Base Suite, which includes ten of Altera’s most popular IP (DSP and memory) cores. The annual software subscription is $2,000 for a node-locked PC license.

New features of Quartus II Version 7.2 include:

  • New State Machine Editor
    Accelerate your design entry with a new graphical state machine design entry tool.
  • New Live I/O Checking
    The addition of real-time pin-out validation allows faster verification of pin placement and assignments.
  • Easier Chip Debug With Enhanced SignalTap® II
    Improved trigger condition settings capture data based on a sequential set of events to allow for faster chip debug. In addition, Signal Tap II offers enhanced segmented acquisition for better use of the memory buffer, allowing for easier hardware verification.
  • Faster Timing Closure With Enhanced TimeQuest
    New clock-as-data feature enables designers to analyze timing when clock signals are used as data, a feature not available in most timing analysis tools. In addition, TimeQuest’s new waveform viewer enables designers to visualize timing relationships for faster timing closure.
  • Improved Avalon® Streaming Support in SOPC Builder
    New automatic insertion of adapters makes finishing your Avalon Streaming designs quicker and easier. In addition, the revamped component editor includes a faster GUI for adding your custom components and support for Avalon Streaming.
  • Expanded OS Support With Windows Vista
    Altera is the only FPGA vendor to support both Windows Vista 32- and 64-bit editions with its Quartus II software.
  • Simplified Software Download
    Altera offers a new unified download and installation for Quartus II Subscription Edition on the Linux operating system to support faster software upgrades.

More info:
Altera Releases Quartus II Software Version 7.2