Altera announced version 7.1 of its Quartus II design software. Quartus II 7.1 offers complete design flow support for the new Arria GX FPGAs. The new version offers more than 2x faster compile times than competitive 65-nm FPGAs. Version 7.1 also includes an enhanced SOPC Builder. The new infrastructure enables a more responsive GUI for faster implementation of large systems and expanded intellectual property (IP) support.
Using advanced place-and-route algorithms, Quartus II 7.1 and Stratix III FPGAs deliver, on average, more than 2X faster compile times when compared to competing high-end 65-nm FPGAs. To further accelerate the design cycle, customers using multi-processor computers see an additional 20 percent reduction in compile times over single-processor computers. Altera’s Quartus II software is the only software from an FPGA vendor offering multi-processor support, taking advantage of today’s dual- and quad-core computers.
The enahanced SOPC Builder automated system development tool features aAn improved infrastructure and a more responsive GUI allows for faster implementation of large systems, and a new Avalon Streaming interface is optimized to send streaming data between two intellectual property (IP) blocks. Quartus II 7.1 also includes a new Avalon Memory-Mapped clock-crossing bridge, a pipeline bridge and a scatter-gather direct memory access (DMA) controller for improved system performance.
Customers can use Quartus II software version 7.1 to design for all members of Altera’s recently announced product families, including Arria GX, Stratix III and Cyclone III FPGAs. With immediate support for the new Arria GX family in both the Subscription Edition and Web Edition of Quartus II software, designers have opportunities to get their PCI Express x1 and x4, Gigabit Ethernet and Serial RapidIO designs to market quickly.
- Faster TimeQuest timing analyzer â€“ Improves productivity with faster timing closure featuring improved compile time, less memory usage and easier conversion from Altera’s classic timing analyzer.
- New compile-time advisor â€“ Recommends compile-time saving settings during the design flow to improve productivity.
- New in-system sources and probes editor â€“ Reduces verification time by allowing designers to drive stimuli to the device and sample internal nodes during run time.
- Expanded synthesis â€“ Provides faster design entry with a new text editor, new HDL templates and true dual-port RAM inferencing.
- Updated parallel flash loader â€“ Offers quicker device configuration with 2X faster flash programming times and burst mode support for flash devices.
- Enhanced usability â€“ Simplifies the design process and accelerates the sign-off process by using the advanced Quartus II message console.
- Smart notification â€“ Automatic notifications via the Quartus II desktop of new software downloads and service packs.
Both the Subscription Edition and free Web Edition of Quartus II 7.1 are available for download. The annual software subscription is $2,000 for a node-locked PC license. Quartus II design software supports major operating systems, including Microsoft Windows XP Professional x64, Microsoft Windows XP and 2000, UNIX (Solaris 8 and 9), Red Hat Enterprise Linux 3.0 and 4.0, and SUSE Enterprise Linux 9.