Altera Corporation (NASDAQ:ALTR) announced version 8.0 of its Quartus® II software. The new version supports the company’s 40nm Stratix® IV FPGAs and HardCopy® ASICs. Quartus II 8.0 software delivers a full two-speed grade advantage and 3X faster compile times for high-end FPGAs when compared to the nearest competitor’s latest offering. Quartus II Subscription Edition software version 8.0 is available now. Both the subscription edition and the web edition of Quartus II software version 8.0 will be available for download on June 2nd. The annual software subscription is $2,495 for a node-locked PC license.
Customers using the 8.0 release to design Altera’s 65-nm Stratix III FPGAs on Windows platforms will see compile times reduced by up to 50%, with an average reduction of 22%, when compared to version 7.2. Users of Linux platforms will see average compile times decrease by more than 30%. Designs leveraging multiprocessor-based servers will obtain an even higher compile time advantage — an additional 20% reduction on average — using the industry’s only vendor-supplied FPGA design software with multiprocessor support.
Quartus II 8.0 Enhancements
- Enhanced TimeQuest Timing Analysis
Faster analysis and debug with expanded reporting and enhanced cross probe capabilities.
- Faster Linux Compilation Times
Improves compilation times on Linux to be on par with compilation times on Windows.
- New Arria GX FPGA Features
Provides added 3.125 Gbps protocol support, including 3G Basic, Serial Lite, SDI, XAUI and CPRI, OBSAI in addition to GIGE, Serial RapidIO® (SRIO) standard and PCIe.
- DSP Builder
Reduce timing closure efforts with the new advanced block set library allowing customers to achieve 30 to 50 percent higher push button performance for a range of digital signal processing (DSP) functions without the need for manual pipelining and folding.
- New Tasks Window
Provides an interactive design flow console that guides users through the FPGA design flow.
- SOPC Builder
Offers support for incremental compilation and adds key intellectual property (IP) blocks to its design library, including JTAG and SPI interfaces.
- Enhanced FPGA I/O Planning
Accelerates board development with added pin-swapping capabilities in the Pin Planner.
- New IP Advisor
Provides design-specific guidelines and recommendations for successful use of Altera’s PCI Express and DDR3 IP.
- MegaCore® IP Library
Integrated in Quartus II software, making it easier for users to access Altera’s portfolio of IP cores. New additions with this release include PCI Express Gen2 hard IP, five new video and image processing cores and many feature enhancements.
- New Megafunctions
New floating point, delay lock loop and memory initialization megafunctions in Quartus II software help speed design development.
More info: Quartus II Software v8.0