Altera Quartus II Software Version 9.0

Altera launched version 9.0 of their Quartus II software for CPLD, FPGA, and HardCopy ASIC development. Version 9.0 supports Altera’s new Stratix IV GT and Arria II GX FPGAs. Altera will separately offer the ModelSim Altera Edition, which was previously available only through a full Quartus II software subscription. The ModelSim Altera Edition delivers to users 33% faster simulation speeds compared to the ModelSim Altera Starter Edition, with no restrictions in design size. A beta version of the Quartus II software version 9.0 is available now. In March, Altera will release the 9.0 production version of Quartus II software, the ModelSim Altera Edition, and the ModelSim Altera Starter Edition. ModelSim Altera Edition will be available for $945 per seat. Quartus II software subscribers receive the ModelSim Altera Starter Edition and a full license to the IP Base Suite, which includes 11 of Altera’s most popular IP (DSP and memory) cores. The annual software subscription is $2,495 for a node-locked PC license.

Quartus II 9.0 Features

  • Expanded Multiprocessor Support
    Altera further reduces compile times by additional parallelization of place and route and synthesis algorithms; the only FPGA vendor to offer multiprocessor support.
  • New Altera Installer
    Faster download and installation of Altera’s software and intellectual property (IP) is now available using the new Altera Installer. The Altera installer provides more granular flexibility to download only what you need.
  • Expanded Verification Support
    With version 9.0, Aldec’s Riviera-Pro simulation tool is now supported offering you the ultimate flexibility when choosing verification tools.
  • New SSN Analyzer Tool
    Provides designer feedback on potential simultaneous switching noise (SSN) violations during pin assignments, enabling faster board design and improving signal integrity.
  • Enhanced SOPC Builder
    Quartus II software further extends productivity advantages with SOPC Builder’s Data Sheet Generator for easier hand-off between hardware and software engineers. In addition, SOPC Builder’s enhanced GUI now offers easier visualization of large systems.
  • Metastability Analysis
    Provides tools to auto-recognize potential metastability circuit issues, and to automate reporting of mean-time-between-failure (MTBF) values as an integrated part of the TimeQuest static timing analysis tool.
  • Pin Planner Enhancements
    A new Clock Network View now available within the pin planner allows designers to better manage clock resources, improving productivity and maximizing performance.

More info: Altera