Xilinx 3GPP LTE Turbo Encoder and 3GPP LTE Turbo Decoder

The 3GPP LTE Turbo Encoder and Decoder LogiCORE, from Xilinx Inc. (Nasdaq: XLNX), are performance-optimized programmable turbo coding solutions for LTE wireless systems. The Xilinx 3GPP LTE Turbo Encoder and Decoder LogiCORE(TM) deliver throughput speeds of up to 200 Mbps with the embedded digital signal processing (DSP) capabilities of Spartan(R) and Virtex(R) field programmable gate arrays (FPGAs) to meet the voice and ever-increasing data communications requirements imposed on modern wireless systems by the evolving long-term evolution (LTE) standard. The new 3GPP LTE Turbo Encoder and Decoder LogiCORE solutions are now shipping with the latest release of the Xilinx CORE Generator(TM) software. They are priced at US$1,500 for the Turbo Encoder and US$15,000 for the Turbo Decoder.

The combination of the Xilinx turbo coding and XtremeDSP(TM) solutions address the throughput demands of 3GPP LTE systems currently in development. The solution meets the system latency reductions proposed in the new LTE standard. The cores are also designed to rapidly adapt to new and evolving requirements, such as the evolution of TD-SCDMA into the proposed TDD variant of LTE.

3GPP LTE Turbo Encoder
The 3GPP LTE Turbo Encoder implements the turbo convolutional encoding scheme defined in the 3GPP LTE specifications. The 3GPP Turbo Encoder can be used in conjunction with the 3GPP LTE Turbo Decoder core. The Encoder contains a full 3GPP LTE interleaver block and supports all 188 block sizes in the 40 – 6144 range permitted by the specification. It is based upon a double-buffered symbol memory scheme for maximum throughput performance, and offers flexible control options to simplify integration into the customer’s system architecture.

3GPP LTE Turbo Encoder Features

  • Fully compliant to the 3GPP LTE specifications
  • Contains 3GPP LTE interleaver
  • Bit accurate C-Model available to speed simulation

3GPP LTE Turbo Decoder
The 3GPP LTE Turbo Decoder is a flexible, high performance and resource efficient implementation of the turbo convolutional decoding scheme defined in the 3GPP LTE specifications. A user specified number of parallel decoders are implemented in order to meet the challenging throughput and latency goals imposed by LTE. An intelligent scheduler optimizes the allocation of decode tasks across these parallel decode units. The 3GPP LTE Turbo Decoder can be used in conjunction with the 3GPP LTE Turbo Encoder core.

The throughput delivered by the Xilinx 3GPP LTE Turbo Decoder LogiCORE solution exceeds the performance of competitive offerings by a factor of five. This enables developers to offload the complex, high-performance decoder function from the rest of the baseband solution, which in turn allows them to use more cost-effective DSP processors for the remaining less performance-critical baseband functions. Developers can also trade-off design size against throughput performance by simply selecting the number of processing units available to the decoder function within the Xilinx FPGA, thus ensuring that only the smallest possible device is needed to meet system performance criteria.

3GPP LTE Turbo Decoder Features

  • Fully compliant to the 3GPP LTE specifications
  • User configurable number of parallel processing units (2, 4 or 8 PUs)
  • Throughput up to 200 Mbps
  • Contains 3GPP LTE interleaver
  • Intelligent scheduler dispatches decode tasks across PUs to optimize throughput and latency
  • Supports MAX, MAXSCALE, and MAX* algorithms
  • Bit accurate C-Model available to speed simulation

More info: 3GPP LTE Turbo Encoder | 3GPP LTE Turbo Decoder