The exorbitant cost of designing and manufacturing ASICs, rapidly evolving standards, the need to reduce bill of materials, and the need for both hardware and software programmability, all in the face of rough economic times and reduced staffing – are converging to create an environment where electronics product designers are increasingly looking to FPGAs as alternatives to ASICs and ASSPs. Xilinx calls the convergence of these trends the Programmable Imperative.
Xilinx is addressing the Programmable Imperative with a 28nm high-performance, low-power process. As a result, engineers will have FPGAs that deliver the ASIC-class capabilities they need to meet their cost and power budgets, while improving their productivity through easy design migration and IP reuse. The FPGA devices will be built on high-K metal gate, high-performance, low-power 28nm processes at Taiwan Semiconductor Manufacturing Company (TSMC) and Samsung Electronics’ Foundry business. Initial devices will be available in the fourth quarter (ISE Design Suite support in June).
At the 28nm node, static power is a very significant portion of the total power dissipation of a device and in some cases is the dominate factor. To achieve maximal power efficiency, the choice of process technology is paramount because the key to enabling greater useable system performance and capabilities is controlling power consumption. Xilinx chose the high-k metal gate high-performance, low-power process at TSMC and Samsung Foundry for next-generation FPGAs to minimize static power consumption.
The new FPGA devices and development tools will form the Base Platform for the next generation of Targeted Design Platforms from Xilinx and 3rd parties. They will include ‘Ultra-High End FPGAs’ that can only be made possible by Xilinx’s process, architectural and tool innovations. Ultra-high-end FPGAs integrate high serial I/O bandwidth, logic density greater than twice that of what is currently in a high-end FPGA, and high-bandwidth interfaces to next generation memory technology. This enables telecommunications system developers to replace a single large ASIC or an ASSP chip set for applications.
Compared to the standard high-performance process, the high-performance, low-power process delivers FPGAs that are 50% lower in static power. The lower static power enables Xilinx to provide engineers with the lowest-power FPGAs in their class, and contributes to a 50% reduction in total power compared to previous generation devices. Meanwhile, next-generation development tools reduce dynamic power as much as 20% through innovative clock management. Enhancements made to Xilinx’s partial reconfiguration technology will enable designers to further drive down power consumption and lower system costs by 33%.
More info: Xilinx