GiDEL PROC_SoC 3-4S and PROC_SoC 10-4S ASIC Prototyping Systems

The GiDEL PROC_SoC 3-4S and PROC_SoC 10-4S ASIC prototyping systems feature the Altera Stratix IV E FPGA. The PROC_SoC 3 and PROC_SoC 10 are designed to debug and verify advanced SoC designs. The PROC_SoC 3-4S supports designs up to 36 million ASIC gates and the PROC_SoC 10-4S supports designs up to 120 million ASIC gates. Both ASIC prototyping systems can be connected to support for up to 360 million ASIC gates. The systems are architected and designed to operate at system clock speeds up to 300MHz.

GiDEL PROC_SoC 10 ASIC prototyping systemsGiDEL PROC_SoC 10 Features

  • Provides scalability for multiple systems to be interconnected
  • Verifies SoC designs with 360 million+ gate
  • Rated capacity of up to 120 million ASIC gates
  • Fast /Gigabit Ethernet communication
  • Operates in an in-circuit emulation mode
  • High performance I/O’s interface to a target or prototype system
  • Up to ten, 6 million/ 12 million gate, reconfigurable PROC6M / PROC12M boards, each with two, interconnected high speed
  • Altera Stratix IV 8200 FPGAs or Stratix III 340 FPGAs
  • Can perform as a single ASIC device at typical system speeds of 35 to 300MHz
  • Enables any FPGA to directly connect to any other FPGA in the same PROC_SoC 10 or other PROC_SoC 10s, through up to six interconnections per FPGA of 118 pins each
  • Additional 261 FPGA-to-FPGA I/O connections on each PROC6M/ PROC12M element and 5 global lines connecting all FPGAs
  • Includes the PROC Developer’s Kit for the efficient mapping of chip designs into PROC_SoC 10 systems, and for debugging designs

PROC_SoC 3 system offers the same features as the PROC_SoC 10, but for smaller application (designs up to 36 million ASIC gates).

GiDEL PROC_SoC 3 ASIC prototyping systems

More info: GiDEL | Kane Computing