Lattice Semiconductor PAC-Designer 5.2

Version 5.2 of Lattice Semiconductor’s PAC-Designer mixed signal design tool suite features new device support and productivity features. PAC-Designer software is the tool suite for the design and verification tool of Lattice mixed signal devices. The PAC-Designer software is a complete design environment, including everything needed for design, implementation, simulation, and programming of supported devices. Lattice’s PAC-Designer software for Windows is available now at no charge for download.

Lattice PAC-Designer 5.2 Features

  • The PAC-Designer 5.2 software now supports two new higher performance Power Manager II products: the ispPAC-POWR1014-2 and ispPAC-POWR1014A-2 devices. The POWR1014/A-2 devices are ideal for integrating Hot Swap control, voltage rail supervision, and power supply sequencing ICs.

  • The PAC-Designer 5.2 software includes an upgrade to the LogiBuilder component, which can now export VHDL or Verilog HDL simulation models of the embedded PLD block of a Power Manager II device. This allows functional verification of sequence and supervisory logic in any popular EDA simulator, including the Aldec Active-HDL Lattice Web Edition simulator. PAC-Designer 5.2 software also supports printing of sequence logic equations directly from the LogiBuilder window.

  • The PAC-Designer software environment makes programmable clock design entry and verification easy, with a graphical block diagram editor for reference clock settings, feedback control and time/phase skew management. PAC-Designer 5.2 software now also provides a graphical skew editor for ispClock 5400D devices.

  • PAC-Designer 5.2 software also supports an expanded input operating frequency range of 40-400MHz for ispClock 5400D devices and a new graphical editor for phase and time skew programming.

Lattice Power Manager II devices integrate programmable analog and PLD technologies to support digital power management solutions. As more digital management functions are integrated, the verification step in the design flow depends on robust simulation technology. The PAC-Designer 5.2 software provides a new VHDL or Verilog HDL export feature to extract simulation models of the embedded PLD block featured on all Lattice Power Manager II family devices. This allows for functional verification of sequence and supervisory logic by the Aldec Active-HDL Lattice Web Edition simulator.

Power Manager II devices are commonly used to integrate discrete ICs for power management such as voltage supervisors, reset generators, watchdog timers and Hot Swap controllers. By adding HDL export features to PAC-Designer software, power supply sequencing, reset signal distribution, and other digital logic integrated into a Power Manager II device can be modeled with IEEE industry standard Verilog HDL or VHDL.

More info: Lattice Semiconductor PAC-Designer 5.2