Ethernity Networks’ ENET architecture enables the support of a full PON OLT line card solution on a single FPGA, due to its inherent support for fragment frames reassembly, GEM header generation, logical queue support per virtual container at ONU side and can support HW acceleration for DBA. The first release of the ENET4000 FPGA Access Flow Processor is designed to fully support OLT EPON or GPON applications, and comes with user side interface selection of 8 x 1Gbps SGMIIs for EPON, or 4x 2.5G SGMII for GPON together with XAUI 10G for backplane / up link connectivity. The ENET4000/PON Access Flow Processor supports all the required Networking and Traffic Management functionalities at 15Gbps, and includes integrated SERDESs for direct connectivity to Fiber Transceivers.
The ENET architecture inherently support most of the PON framer functionality on the same FPGA without the need to add more logic, thus enable the support of a full PON OLT line card solution on a single FPGA.
- GPON frames Reassembly
The ENET is a fragment frame switch and as part of this inherently can perform the entire GPON frame reassembly without the need for additional logic
- GEM Header
The ENET architecture include wirespeed packet editor , which can support any Ethernet Header and Encapsulation, together with stamping bit/bytes any where in the header, which can be used to stamp grant or gate messages
- Logical Egress port queues
The ENET hierarchical scheduler can maintain queue per flow, hence inherently can maintain queue per remote ONU
- Identify DBA information
The ENET field decoding engine can decode any data within incoming frame
The ENET4000 will start field trials at customer product during April/08 and is now available for immediate design for new customers. Design kit includes full software solution, schematics, data sheet and ATCA evaluation board equipped with 8 SGMII ports , or 4 x 2.5G SGMII, together with two 1+1 10G XAUI interfaces. The evaluation board can be ordered and is available for customer evaluation and tests.