PLDA Unveils QuickTCP 10G TCP/IP Stack IP Core for Altera, Xilinx FPGA
PLDA recently introduced their QuickTCP IP, which is a 10Gb TCP/IP Hardware stack IP core. It features an AMBA AXI4 user interface that enables instant integration into either Altera-based or Xilinx-based FPGA designs. PLDA QuickTCP is a 100% RTL designed IP. It is compliant with the IEEE802.3 specification and supporting the ARP, IPv4, ICMP, and TCP protocols. The PLDA QuickTCP IP solution is available now from PLDA.
PLDA’s QuickTCP IP features extremely low latency of less than 150ns to the FPGA fabric, and its highly scalable architecture provides a seamless migration path to 40G and beyond. When combined with the PLDA QuickPCIe AXI4 based PCI Express Gen3 with DMA IP core and its latency-optimized Linux device driver, the 10G wire to user space latency is under 1.5µs.
PLDA QuickTCP Key Features
- Full RTL layers 2, 3, 4 implementation
- Integrated layer 1 PHY interface for Altera Stratix IV, Stratix V and Xilinx Virtex-7, Kintex-7 FPGA
- Supports Client and Server mode
- Supports up to 16 TCP sessions, easily scalable to 64 sessions or more
- Easy to use standard-based user interface (AXI Streaming / AXI Lite)
- Integrated TCP Options Management (MSS, Window Scaling, Timestamps) and flexible management interface
- Hardened ICMP and ARP
- Standard MTU (1500 and 9000)
- VLAN configurable at runtime
- Fully configurable Retry memory (internal or external DDR/QDR/RLDRAM)
More info: PLDA
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