PLDA PCIe 2.0 IP Core for Xilinx Virtex-5 FXT FPGA
PLDA announced PCIe Gen 2 FPGA IP support for the Xilinx’s Virtex®-5 FXT platform. The PLDA PCIe IP Core is 100% compliant with Revision 2.0 of the PCIe specification and supports both x1 and x4 configurations. The Xilinx Virtex-5 FXT devices are the industry’s first FPGAs with embedded PowerPC440 processor blocks, high-speed RocketIO(tm) GTX transceivers and dedicated XtremeDSP(tm) processing capabilities, offering designers high levels of system integration and performance. Each processor, with integrated 32KB instruction and 32KB data caches, delivers up to 1,100 DMIPS at 550 MHz. Tightly coupled to the PowerPC440 blocks is a new, integrated 5×2 cross bar processor interconnect architecture that provides simultaneous access to I/O and memory for high system throughput.
KPLDA PCIe Gen 2 IP Core Key Features
- Application layer with up to 8 automated DMA engines
- High performance interface allows up to 16 simultaneous outstanding requests
- Complete support for scatter-gather
- User interface similar to PLDA’s EZ DMA IP (DMA Application layer designed to work with the Virtex-5 family’s embedded endpoint block)
If you are familiar with RSS feeds, you can also sign up for our free blog feed. Our RSS feed is updated in real-time while our newsletter is updated daily.
