Xilinx (Nasdaq: XLNX) PlanAhead(TM) v9.2 features expanded functionality of Xilinx(R) PinAhead technology. PinAhead technology provides FPGA designers with the ability to assign interface I/O groups to I/O pins simply by dragging into a graphical representation of the FPGA. PlanAhead 9.2 software further simplifies the complexities of managing the interface between the designer’s target FPGA and the PCB with the ability to import and export I/O port information through VHDL or Verilog headers.
PlanAhead 9.2 software supports Xilinx’s latest low-cost Spartan(TM)-3A DSP platform FPGA. PlanAhead now supports the entire line of Xilinx(R) Spartan(TM)-3 generation FPGAs.
PinAhead technology facilitates early and intelligent pinout definition to eliminate many of the pinout related changes that typically happen downstream. Better user control of FPGA pinout early in the design process also offers significant improvements in performance, avoiding a non-optimal pinout which causes further delays when trying to meet timing requirements. By considering the data flow from PCB to FPGA die, optimal pinout configurations can be achieved quickly, thus reducing internal and external trace lengths and routing congestion.
During the pin planning process, PlanAhead 9.2 software allows users to better explore pinout information with extended reporting capabilities. PlanAhead 9.2 software can now display more information about the I/O ports assigned to individual I/O banks. Users can select an I/O Bank to view the values for VCCO, VREF, and I/O STANDARD. Users can also display the number of I/O Ports assigned to the I/O Bank and the number of remaining available pins for assignment.
PlanAhead 9.2 provides an environment where users can better investigate individual clock regions by displaying information about the various I/O banks contained in each clock region. Users can also create their own port list with a GUI interface or import a comma separated values (CSV) spreadsheet. Through these multiple options, PlanAhead 9.2 software enables early decisions to be made, permitting PCB and FPGA designers to begin work much earlier with a much more realistic pinout configuration.
PlanAhead 9.2 software is available on all major operating systems as an option to the Xilinx(R) ISE(TM) design suite. Single-user licenses are currently available at a promotional price of at $2,495 US list.