The 09.03 release of the Synfora PICO Extreme FPGA C synthesis tool supports the Xilinx Spartan-6 and Virtex-6 devices. It also integrates seamlessly with the Xilinx Embedded Development Kit (EDK) tool suite. In addition, version 09.03 of PICO Extreme FPGA provides improved quality of results with area and throughput improvements of up to 15%. Version 09.03 of PICO Extreme FPGA and PICO Extreme are now available.
Pico Extreme FPGA enables traditional DSP programmers to more easily migrate their existing applications to Xilinx FPGAs and the new integration with the Xilinx embedded environment allows our customers to take advantage of Synfora”s high quality C-to-FPGA design flow when targeting our embedded and video development platforms.
The 09.03 release of the PICO Extreme FPGA supports the next-generation Xilinx Spartan-6 and Virtex-6 devices. Designers can select a specific Spartan-6 or Virtex-6 part as the target device, and PICO Extreme FPGA will generate RTL optimized for that device in terms of area and performance, including optimal use of block RAMs and DSP48 slices, based on a detailed knowledge of the device characteristics.
The new release also supports integration with the Xilinx Embedded Development Kit (EDK) tool suite to enable the design of a complete embedded processor system for implementation in a Xilinx FPGA device. Designers can direct PICO Extreme FPGA to export designs as custom embedded peripherals that can be easily imported into the Xilinx embedded development environment and integrated with other IPs including a MicroBlaze processor core to create processor-based designs. It also allows users to interface to streaming communication protocols like FSL and LocalLink as well to DDR memory.
The new version of PICO Extreme FPGA also provides improved quality of results based on algorithmic and flow enhancements in the scheduler as well as several new techniques to reduce the number of registers. On a suite of customer FPGA designs, these enhancements to PICO improved design area by 7 percent to 15 percent and throughput by 11% to 15%.
PICO Extreme FPGA extends high level synthesis technology to FPGA devices, enabling the implementation of dramatically larger and more complex FPGA sub-systems, such as video codecs, wireless modems and imaging pipelines, from untimed C algorithms with quality of results comparable to manual designs. It is based on an advanced optimizing compiler that transforms a sequential, untimed C algorithm into highly efficient RTL (Register Transfer Language), reducing design and verification time, allowing designers to find the lowest cost implementation and enabling very rapid response to changes in the design specification. Using untimed C as the design entry language decreases design and verification time as well as improves design reuse across multiple device architectures.
More info: Synfora