Altera Unveils Direct Memory Access Reference Design for Stratix V FPGA

Altera introduced a direct memory access (DMA) reference design. The solution is constructed for Stratix V customers needing to seamlessly and quickly design PCIe Gen3 solutions. Stratix V GX FPGAs feature a hardened protocol stack for PCIe Gen3 applications, demanding the highest in bandwidth, system integration and flexibility, at a reduced cost with lower total power consumption. The new DMA reference design makes it fast and easy to develop high-performance PCIe Gen3x8 hardware.

Altera DMA Reference Design Features

  • Linux driver that works with the example design
  • Peak throughput (142 cycles of 256-bit at 250MHz)
  • 7.1 GB/s: back to back Tx memory write 256 byte payload
  • 7.0 GB/s: back to back Rx read completion throughput
  • Simultaneous read/write: 11.4GB/sec

The direct memory access reference design highlights the capabilities of Stratix V designs that require PCIe Gen3x8. By demonstrating peak bandwidth of the theoretical maximum, the reference design shows that Altera’s Gen3 solution can preserve almost all the bandwidth available in Gen3 systems or at Gen3 data rates. In addition, by demonstrating simultaneous read/write at upwards of 11 GB/sec, the design shows how much bandwidth customers can take advantage of in a real-world implementation.

More info: Altera Corporation