According to Xilinx, the Spartan-6 FPGA family is compliant with the PCI Express 1.1 specification. Spartan-6 FPGAs offer a low cost PCIe implementation for programmable devices with twice the capability and less than half the power of previous Spartan-3 generation two-chip offerings. Developers can now design PCIe compliant systems based on the connectivity requirements of their applications and not be constrained by the cost of silicon. Spartan-6 FPGAs are ideal for developing systems compliant with PCIe for applications such as in-vehicle infotainment, flat-panel displays, and video surveillance.
The integrated Endpoint block for PCI Express in Xilinx Spartan-6 LXT FPGAs has passed PCI-SIG compliance and interoperability testing for PCIe 1.1 single-lane configurations. Xilinx was the first to integrate compliant PCIe version 1.1 blocks into programmable devices with its Virtex-5 FPGA family, and the first to introduce a FPGA offering compliant with the 5Gbps version of PCIe 2.0 standard with soft IP support in Virtex-5 FXT and Virtex-5 TXT devices.
PCIe 1.1 is implemented in Spartan-6 LXT devices with production-proven Xilinx GTP serial transceivers capable of up to 3.125Gbps and the LogiCORE solution using the integrated Endpoint block for PCI Express. The configurable PCIe core with physical layer (PHY) is the lowest-cost, single-lane integrated programmable implementation available today. The GTP serial transceivers are fully characterized across process, voltage, and temperature (PVT).
The Spartan-6 FPGA integrated Endpoint block for PCI Express incorporates many easy-to-use features to simplify the design process as well as configurations optimized for PCIe Endpoint applications. It is also supported with additional design resources for creating complete PCIe solutions.
More info: Xilinx Spartan-6 FPGA Family