The Xilinx Virtex-6 FPGA family is now compliant with the PCI Express 2.0 specification. The second-generation PCIe block integrated in the Xilinx Virtex-6 FPGA family has passed PCI-SIG PCI Express version 2.0 compliance and interoperability testing for 1 to 8-lane configurations. The PCIe 2.0 standard is critical to meeting the requirements of high performance, low power applications for communications, multimedia, server and mobile platforms. Integrated PCIe FPGA blocks eliminate the I/O bottleneck in maximizing system performance.
PCIe 2.0 blocks are integrated in all Virtex-6 devices with serial transceivers and are supported in all speed grades. These blocks include the complete transaction data link and physical layers, which use the Xilinx GTX transceiver technology and integrated BRAM. The GTX serial transceivers in Virtex-6 LXT and SXT FPGAs are fully characterized across process, voltage and temperature (PVT).
The Virtex-6 FPGA Endpoint block for PCI Express includes many easy-to-use features to simplify the design process, as well as configurations optimized for PCIe Endpoint and Root Port applications with additional resources to create a complete PCIe solution. In addition, Xilinx has teamed up with Northwest Logic and PLDA to provide Direct Memory Access (DMA) intellectual property (IP) cores for Virtex-6 FPGAs. DMA engines enable the efficient movement of data in systems, ensuring that the PCIe block in Virtex-6 FPGAs delivers maximum performance and bandwidth.
Designers can immediately begin the evaluation and design of PCI Express 2.0 compliant systems in Virtex-6 FPGAs. The Xilinx CORE Generator system delivered in the ISE Design Suite provides the PCIe core, reference design, scripts, basic testbench, and simulation models needed to streamline integration into designs.
More information: Xilinx PCI Express Solutions