The Altera 40nm Arria II GX FPGAs are offically compliant with the PCI Express (PCIe) 2.0 specification. The Arria II GX device successfully passed the PCI-SIG Compliance and Interoperability Tests at the PCI-SIG Workshop and is now included on the PCI-SIG Integrators List. Arria II GX FPGAs achieved compliance for up to x8 lane configurations for PCIe Gen1 end-point applications. Altera’s Arria II GX FPGAs feature integrated transceivers with data rates up to 3.75 Gbps, and have a hard, configurable PCIe interface embedded within the device. The device’s hard IP block implements PCIe Gen1 (PIPE) PHY-MAC, data link, and transaction layers. The IP block is highly configurable to meet the requirements to support end-point and root-port applications, and is PCIe 2.0 compliant in x1-, x4- and x8-lane configurations.
More information: Altera