Lattice Semiconductor rolled out version 6.2 of their PAC-Designer mixed signal design software. PAC-Designer 6.2 features updated support for Lattice’s Platform Manager, Power Manager II and ispClock devices, reduced LogiBuilder code size, simplified design flow and better access to external Platform Manager pin-to-pin connections. PAC-Designer v6.2 can be downloaded now for free. PAC-Designer 6.2 software does not require a separate license file.
Engineers designing with Platform Manager devices now have more integrated access to the Lattice Diamond 1.4 software design environment. The advanced integration of the PAC-Designer v6.2 and Lattice Diamond v1.4 design software tools result in more advanced digital design options available for Platform Manager products.
PAC-Designer v6.2 Features
Comprehensive Analog and Digital Design Flow
Offers an easy to use GUI-based design methodology for configuring the Platform Manager’s analog sections. To implement more advanced digital board management functions, Lattice Diamond Verilog/VHDL design tools are available for use with the same design. Once a design is implemented, a complete simulation environment is created that includes automatic stimulus template file generation.
Includes reference designs specifically targeted for the Platform Manager development kit. More reference designs compatible with Platform Manager devices are also available.
Third Party Design Tool Support
The integrated PAC-Designer 6.2 and Lattice Diamond 1.4 software both include the Synopsys Synplify Pro advanced FPGA synthesis for Windows. Aldec’s Active-HDL Lattice Edition II simulator is also included for Windows. In addition to the tool support provided by the OEM versions of Synplify Pro and Active-HDL, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support Lattice devices.
More info: Lattice Semiconductor