Lattice PAC-Designer Mixed Signal Design Software, Version 6.1

Lattice Semiconductor introduced version 6.1 of their PAC-Designer mixed signal design software. PAC-Designer v6.1 features updated support for Lattice’s Platform Manager, Power Manager II and ispClock devices. The tool is also now integrated with Diamond 1.3 design software tools to increase digital design options for Platform Manager products. PAC-Designer 6.1 is available now for free download. Once downloaded and installed, PAC-Designer 6.1 software requires no license.

PAC-Designer v6.1 Highlights

  • Integrates seamlessly with Diamond 1.3 design tools
  • Design flow has been optimized and automated
  • Compiles the entire design, creates the necessary stimulus template file and then automatically generates initial timing waveforms within the Aldec Active-HDL simulator
  • With a click of the mouse, tool generates all the necessary design files and creates the initial timing flow diagram
  • GUI-based design methodology for analog engineers
  • Intuitive dialog boxes to configure the Platform Manager’s analog sections
  • LogiBuilder design methodology to integrate power management functions into the on-chip CPLD
  • LogiBuilder or Lattice Diamond Verilog/VHDL design methodology to integrate digital board management functions into the FPGA section of the Platform Manager device
  • Includes four reference designs for the Platform Manager development kit (Fault Logging and Monitoring, Enhanced Closed-loop Trim, Long Delay Timers and ADC Voltage Measurement)
  • Eleven additional reference designs compatible with Platform Manager devices are available on the Lattice website
  • Thirty-one additional design examples are also available from directly within PAC-Designer 6.1 software
  • Includes the Synopsys Synplify Pro advanced FPGA synthesis for Windows
  • Aldec’s Active-HDL Lattice Edition II simulator is also included for Windows

More info: Lattice Semiconductor