IEEE 1588 Clock Synchronization for Lattice FPGA
Today Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the availability of Industrial Ethernet Intellectual Property (IP) from Oregano Systems Design and Consulting. Oregano ported their IEEE 1588 IP core for clock synchronization over Ethernet to the LatticeXP(TM) and LatticeXP2(TM) FPGA families. Oregano’s IP core implements a popular IEEE standard that is used for many Industrial Ethernet applications to ensure that the various nodes in a network have synchronized real time clocks. The solution can be delivered as a standard IP core or Oregano can program it onto a LatticeXP or LatticeXP2 device and deliver it as an Application Specific Standard Product (ASSP).
Oregano Systems’ SYN1588 IP cores are compliant with the IEEE 1588 clock synchronization standard. Each core implements a local high speed, high resolution clock, which is attached to the MII — the interface between the physical layer IC and the MAC — via a so-called time stamping unit. All SYN1588 products are bundled with the respective PTP stack and driver software, enabling the customer to integrate the core with little effort. The SYN1588 IP core is available in netlist format for the non-volatile, instant-on LatticeXP and LatticeXP2 FPGA families. The IP cores are configurable for serial or parallel interfaces, as well as a number of trigger inputs and clock outputs. All IP cores are completely verified by Oregano to 100% code coverage and are shipped with automated test benches.
More info: Lattice Semiconductor | Oregano Systems Design and Consulting
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