XPressArray-II Structured ASIC for Military and Aerospace Applications

ON Semiconductor (Nasdaq:ONNN) announced that XPressArray-II (XPA-II) structured ASIC technology is now available for military specification operating temperatures (as the M-XPA-II Family). By providing operation across the full military operating temperature range of -55°C – 125°C, XPA-II provides military and aerospace manufacturers with a cost-effective route to creating leading-edge ASICs and FPGA-to-ASIC conversions with minimum time to market. On-shore production and full ITAR compliance is assured through all stages of the development process, from initial design through to back-end packaging and test.

XPA-II is targeted at medium-density, high-speed 1.5V ASIC applications and FPGA-to-ASIC conversions. The structured ASIC family offers a true drop-in alternative for a variety of FPGAs, including Altera APEX-II and Stratix technologies and Xilinx Virtex-II solutions.

Based on a hybrid fabrication process, XPA-II combines advanced 0.15-micron TSMC process technology with programmable metal using ON Semiconductor’s own state-of-the-art manufacturing facilities. The result is an innovative next-generation technology platform that dramatically reduces development time for system-on-chip (SoC) applications while delivering significant NRE (non-recurring engineering costs) and unit cost savings.

Operating with system clock speeds up to 210MHz for 18×18 soft multipliers and local clocks up to 500MHz, XPA-II 0.15µm devices deliver high performance, low power ASIC solutions with densities to 4.8M ASIC gates. Configurable memory ranges from 258kbits to 4.8Mbits, increasing to 6.1Mbits with the addition of distributed configurable memory.

The XPA-II I/O technology includes fully configurable signal, core and I/O power supply pad locations and support for a wide range of I/O standards, including PCI, PCI-X, Mode 1 and Mode 2, GTL, HSTL, SSTL and LVPECL. The I/O technology also features a double data rate (DDR) memory interface and 1Gbps low-voltage differential signaling (LVDS). All of these features are available in a platform that supports power dissipation of just 55nW/MHz/gate, reducing total chip power consumption to less than 20 percent of a standard FPGA. High fault coverage is provided through integrated scan-test, memory BIST and JTAG support.

More information: ON Semiconductor