Altera Stratix V GT FPGA Interoperates with 100-Gbps Optical Module

Altera recently used their 28nm Stratix V GT FPGA devices to demonstrate interoperability with a 100-Gbps optical module. This is the first time a field programmable gate array has demonstrated interoperability with a 100-Gbps optical module. The Altera Stratix V GT FPGA’s interoperability with 100-Gbps optical module will enable next-generation 100-Gbps networks. This is of importance because more bandwidth will be required in the next few years because global Internet traffic expected to multiply dramatically.

Altera’s Stratix V GT FPGAs are designed to support 25- to 28-Gbps data streams for next-generation 100-Gbps pluggable fiber-optic modules, line cards and direct-attach copper cables using the 25G-QSFP+ and CFP2 form factors. The devices feature excellent jitter performance with low power consumption.

Stratix V devices offer the highest system bandwidth at the lowest power consumption. The FPGA consumes less than 200 mW per channel at 28 Gbps. Altera Stratix V FPGA devices support backplane, optical module and chip-to-chip applications through 28 Gbps transceivers, and up to 66 full-duplex 14.1-Gbps transceivers. The 28-Gbps integrated transceivers in Stratix V GT FPGAs offer the industry’s highest system reliability with the lowest jitter.

Altera will demonstrate Stratix V GT FPGA’s interoperability with 100-Gbps optical module at the upcoming Optical Internetworking Forum (OIF). The demonstration includes four channels of PRBS31 data generating within the Altera’s Stratix V FPGA, which is tailored to support the most bandwidth-intensive communications systems. The data is then transmitted over a Gennum VSR host channel with 12 dB of insertion loss, through a Molex zQSFP+ connector to Gennum clock and data recovery (CDR) integrated circuits. The retimed outputs of the CDRs are transmitted to the Molex 1490-nm Optical Module, which loops the optical data back to its receiver through 2 km of SM fiber. In the receive direction, the data flows in the reverse order through the cascaded blocks ending at the FPGA. The error checkers within Altera’s FPGA verify that the entire transmit and receive data path through the system is operating error free.

More info: Altera Corporation