Altera and Apical introduced the first high-definition wide dynamic range (WDR) CMOS image-sensor-processing solution for video-surveillance cameras. Altera and Apical’s reference design delivers excellent video-image quality regardless of varying lighting conditions, a major stumbling block for previous generations of surveillance cameras. The HD WDR CMOS image sensor features Altera’s Cyclone III and Cyclone IV FPGAs, and Apical’s intellectual property (IP). The reference design supports Aptina’s new MT9M033 High-Definition WDR CMOS image sensor.
Standard CMOS image sensors are limited by the vast ranges of brightness levels, from low light to direct sunlight, that can black out or wash out a video subject. WDR CMOS image sensors correct this problem, but present a design challenge. The large amounts of data (up to 20 bits per color x 1.2 Mpixels at 60 frames per second) generated by these image sensors must be processed in the Image Sensor Pipeline (ISP), but are too much to be handled on-chip. The DSPs and ASSPs typically used in surveillance systems do not have the ability to handle the processing task efficiently. Altera’s Cyclone FPGAs have the capability to perform the intense number-crunching algorithms that convert the raw image data into a standard digital output needed to produce a clear video image.
The sensor processing design implemented in the FPGA is provided by Apical. The IP from Apical includes the full ISP, which performs the auto-exposure, auto-gain, and auto-white balancing that contribute to clear video images in extreme low-light and bright-light conditions. Apical’s IP also optimizes video images by incorporating Apical’s state-of-the-art iridix local tone mapping engine, which mimics the human eye, with high performance 2D or 3D noise reduction, and advanced color processing. The Cyclone III and Cyclone IV families of FPGAs perform all of these functions at industry leading clock rates, logic utilization, and power consumption.