Lattice PAC-Designer 5.0

Lattice Semiconductor launched PAC-Designer 5.0 mixed signal design tool suite. The PAC-Designer 5.0 software supports the new ispClock 5400D family of in-system programmable ICs, which are ideal for applications that require low-cost SERDES clock references and distributing high speed differential clocks. Lattice’s PAC-Designer tool suite is the design and verification tool for Lattice ispPAC devices. PAC-Designer software for Windows is available now at no charge.

PAC-Designer 5.0

  • ispClock5400D Design Support
    The PAC-Designer environment makes ispClock5400D design entry and verification easy with an interactive graphical user interface schematic diagram, which provides access to all ispClock device options such as reference frequency, output buffer driver type and divider settings. Programmable analog blocks, like the FlexiClock I/Os and CleanClock PLL of the ispClock5400D device are easily modified to accommodate a variety of circuit board requirements.

  • Improved Quality of Results
    Lattice ispPAC Power Manager devices integrate programmable analog and PLD technologies to support digital power management solutions. The PAC-Designer 5.0 software includes an upgrade to the LogiBuilder component, which can reduce the logic consumption of PLD core macrocell resources 20-30%. LogiBuilder now supports sequencer instructions with concurrent output expressions. This instruction style can dramatically reduce the number of macrocells required to implement the embedded state machines used for intelligent power sequencing.

More info: Lattice Semiconductor PAC-Designer Software