Bluespec to Demonstrate Synthesizable Model and Testbench

At the Design Automation Conference (DAC), Bluespec[tm] Inc. will demonstrate a synthesizable model and testbench that run at 35,000 times faster than event-based simulation. Bluespec will also showcase its new development workstation in Booth #2367. Bluespec’s hardware demo will show an FPGA-based implementation — including hardware transactors, a synthesizable testbench, high-level models ,and AXI bus components.

Rishiyur Nikhil, Bluespec’s chief technical officer, will present “From Executable Specifications to High-quality Implementations Using Bluespec,” June 8th, from 9:00 a.m. – 9:20 a.m. at the workshop, “High-Level Synthesis: Back to the Future,” in room 208A. Professor Arvind, Bluespec co-founder and board member, will present “HLS as an Enabling Technology: Some Complex Examples” from 1:30 p.m. – 1:50 p.m. at the same workshop.

Rishiyur Nikhil will also be chairing session 23, “Architectural and Precision Optimization in High-Level Synthesis” on Wednesday, June 11th, from 9:00A-11:00A in room 210AB.

At the MEMOCODE 2008 conference, which is collocated at DAC, Professor Arvind and Rishiyur Nikhil will be giving a tutorial entitled “Hands-on Introduction to BSV (Bluespec SystemVerilog)” on Saturday, June 7, 2008, in room 303B.

More info: Bluespec | MEMOCODE 2008 Conference