Fujitsu Microelectronics America announced the DKXC5VADAPT-1 digital-to-analog (DAC) converter development kit adaptor. The DKXC5VADAPT-1 is designed to create a compact solution for developing and testing an FPGA-DAC interface. The DKXC5VADAPT-1 features a high-performance interface, the Xilinx Virtex-5 FPGA, and the Fujitsu high-speed MB86064/5 DAC. The MB86065 is a 14-bit, 1.3GSa/s, single-channel DAC derived from the MB86064 dual 14-bit, 1GSa/s DAC. The Fujitsu DKXC5VADAPT-1 DAC development kit adaptors are available now.
Fujitsu DKXC5VADAPT-1 DAC DK FPGA Adaptor
- LVDS data interface for one (MB86065) or two (MB86064) DAC cores
- Loop Clock system for optimum timing
- GPIO to FPGA
- Support for single-supply operation: voltage regulators to provide the DAC supply voltages (1.8V and 3.3V) using the 5V supply for the V5-PCIE2 board
- Socket to allow connection to the DK serial programming header, eliminating the need for an external serial programmer to program the DAC
The DKXC5VADAPT-1 kit adaptor provides a physical link between the data headers on the Fujitsu DK86064-2 and DK86065-2 development kits and the HiTech Global V5-PCIE2 FPGA prototype board. The adaptor features six Samtec sockets that plug into the headers on the two boards, connecting 28 matched LVDS data pairs, the DAC Loop Clock pairs and two divided clock signals between the two boards. All clock signals are routed to dedicated global clock inputs on the FPGA.
The Hi-Tech Global V5-PCIE2 development platform features tri-mode Ethernet (10/100/1000), a 4-lane PCI Express end-point connector (upstream), and a DDR2 SO-DIMM socket (up to 4GB). The platform also includes a 512MB DDR3 component, 128MB Platform Flash XL for configuration, user Flash memory and on-board clocking.
The DKXC5VADAPT-1 comes with example firmware and, once combined with the appropriate Fujitsu DAC development kit, creates a compact platform that covers all aspects of the FPGA/DAC interface design.
The Fujitsu MB86064 and MB86065 DACs maintain valid clock-to-date timing by using a proprietary Loop Clock system. The Loop Clock is generated in sync with the DAC data at the FPGA output. The clock is passed through a user-programmable delay in the DAC, and then routed back to the FPGA’s PLL feedback input. Altering the delays in the divided clock or Loop Clock signals allows the user to advance or retard data timings to find the optimal data eye. Once calibrated, the system automatically compensates for the effects of device-to-device variations in phase, voltage and temperature (PVT).
More info: Fujitsu DKXC5VADAPT-1 DAC DK FPGA Adaptor (pdf)