Altera, Arrow Electronics, and MathWorks to Host DSP Forum

Altera, Arrow Electronics, and MathWorks are hosting the DSP Forum. The event will discuss application-specific digital signal processing design methodologies targeted for Altera FPGAs. DSP Forum will also explain how the combination of DSP Builder’s model-based design flow and MathWorks tools helps implement high-performance floating-point DSP. The one-day event will take place in multiple cities from May 1st to June 7th.

Experts from the military, wireless, video and industrial sectors will discuss how the Model-Based Design flow supported by Altera’s DSP Builder, together with MATLAB, Simulink, and HDL Coder from MathWorks, can help engineers implement high-performance floating-point DSP algorithms. In addition, DSP Forum will discuss Altera’s video design framework and video IP solutions.

DSP Forum Dates and Locations

  • Chicago, May 1, 2012
  • Dallas, May 3, 2012
  • Boston, May 22, 2012
  • Baltimore, May 24, 2012
  • San Jose, June 5, 2012
  • Los Angeles, June 7, 2012

DSP Forum Topics


  • Introduction to radar system modeling via:
    • MATLAB and Simulink
    • Phased Array System Toolbox
    • DSP Builder Advanced Blockset
  • Radar processing demo design
    • Single-precision floating point
    • Pulse compression
    • Moving target indication (MTI)
    • Radar corner turn (modeling external DDR memory operation and bandwidth)
    • Doppler processing and interpolation
    • Detection
  • Floating-point implementation and demonstration


  • Basics of CFR and DPD
  • Introduction to CFR modeling via:
    • Simulink
    • DSP Builder Advanced Blockset
  • CFR algorithm theory and implementation
    • Peak-to-average ratio (PAR) and adjacent channel leakage ratio (ACLR)
    • Peak windowing algorithm techniques
    • Peak detection and selection
    • Peak cancellation pulse scaling and generation techniques
    • Iterative peak cancellation
    • Full testbench including multicarrier Code Division Multiple Access (CDMA) signal generation and measurement of PAR, ACLR, complementary cumulative distribution function (CCDF), and error vector magnitude (EVM)
  • Implementation and demonstration
    • Crest Factor Reduction
    • Digital Up Conversion techniques
    • Digital Up Conversion example up to 4 Giga-Sample per Second (GSPS)


  • Basics of video processing
    • Interfaces
    • Processing functions including scaling, deinterlacing, and alpha blending
  • Introduction to Altera’s complete video solution: video design framework
    • Bundled IP cores
    • Video streaming interface
    • Pre-verified video reference designs
    • Video development kit portfolio
  • Steps to integrate video interface, debug, and processing functions on Altera FPGAs
  • Demonstrations
    • Video and Image Processing (VIP) Suite design example on the Video and Embedded Evaluation Kit (VEEK)
    • 1080p reference design with video debug feature
    • Custom IP integration


  • Modeling control systems with Simulink
  • Basics of motor control theory
    • Magnetic field theory
    • Field-oriented control (FOC) and Park and Clarke transforms
    • Types of motors
  • Using simulation to design and test motor control algorithms before hardware is available
  • Implementing motor controllers in FPGAs using MathWorks HDL Coder and Altera DSP Builder Advanced
  • Blockset
  • Comparison of fixed- and floating-point implementations in Altera Cyclone devices
  • Motor control demonstrations:
    • Park and Clarke transforms
    • PI controller
    • Space vector modulation

More info: DSP Forum