Lattice Semiconductor Debuts Serial sub-LVDS Bridge Design for Sony IMX136, IMX104 Image Sensors
Lattice Semiconductor introduced a serial sub-LVDS bridge reference design for the Sony IMX136 and IMX104 image sensors. Lattice’s image sensor bridge design helps engineers quickly introduce cameras based on the Sony IMX136 and IMX104. The image sensor bridge design is available now for download, and the MachXO2-1200 (featured in the reference design) is in full production.
Lattice’s new image sensor bridge design features the MachXO2 PLD. The programmable logic device interfaces to the serial sub-LVDS bus of the Sony IMX136 or IMX104 image sensor. External discrete components are not needed because the Lattice MachXO2-1200 PLD interfaces directly to the sub-LVDS I/Os.
The image sensor bridge design enables an ISP (Image Signal Processor) with a CMOS parallel interface bus to connect to the Sony IMX136 or IMX104. The image sensor bridge application can support 1080P60 resolution with a 12-bit ISP interface. If needed, the design code in the MachXO2 device can be easily modified for the full 1080P120 capability of the Sony IMX136 or IMX104. The design is ideal for surveillance cameras, video conferencing and industrial cameras.
Lattice Semiconductor also has a reference design that supports the legacy Sony parallel sub-LVDS DDR format. The Lattice MachXO2-1200 or the Lattice XP2-5 non-volatile FPGA provides an efficient and cost-effective solution for bridging parallel sub-LVDS.
Lattice sub-LVDS to Parallel Sensor Bridge Features
- Complete reference designs in MachXO2-1200 or XP2-5
- Designed to emulate parallel sensor output bus width of 10 or 12 bits
- Serial sub-LVDS interface to CMOS SDR data
- Legacy sub-LVDS parallel DDR to CMOS SDR also available
- Tested with Sony IMX036 and TI DM812X at 1080p60
- Converts the sub-LVDS sync commands to line valid and frame valid signals
- Bridge device offered in space-saving 8×8 mm 132-Ball csBGA
- TQFP packages also available
- Requires no external PROM
- Parallel interface can be configured for 1.8V, 2.5V or 3.3V LVCMOS levels
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