Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the availability of its third generation non-volatile FPGAs, the LatticeXP2(TM) family. With enhanced capabilities, the LatticeXP2 family doubles maximum logic capacity to 40K Look Up Tables (LUTs), improves performance 25% and adds dedicated DSP blocks, all while reducing the price per function by up to 50%. Power consumption has also been optimized on the 1.2-volt process technology, reducing static power usage by 33%. Designed using the industry’s most advanced non-volatile FPGA technology, a 90nm embedded Flash process co-developed with Lattice’s foundry partner Fujitsu, the LatticeXP2 devices provide the “instant-on” and reduced footprint benefits of earlier Lattice non-volatile devices, while also enhancing design security, RAM back-up and live update capabilities.
The LatticeXP2 family consists of five members, with capacities from 5K to 40K 4-input Look Up Tables (LUTs). Embedded block memory provides up to 885Kbits in 18Kbit dual port blocks. For small scratch pad memories, LUTs can also be converted into small, distributed memory blocks. To support increasingly common DSP applications, up to 12 sysDSP(TM) blocks provide hardwired high-performance pipelined multiply and accumulate functions. The devices have up to four Phase Locked Loops (PLLs) that allow designers to align and synthesize clocks as required in their designs.
With power consumption such an increasing concern today for system designers, Lattice designed the LatticeXP2 family to use a 1.2-volt core voltage for low power consumption. In addition, the circuit design was tuned to reduce static power per logic function by approximately 33% overall. This means that while the largest device density has doubled to 40K LUTs compared to the 20K LUTs on the largest LatticeXP2 density, the static power consumed by the largest LatticeXP2 family member has increased by only 34%.
I/O capacities for the family range from 86 to 540 pins. Flexible I/O buffers support the most popular I/O standards, including LVCMOS, SSTL, HSTL and LVDS. These buffers are supported by pre-engineered I/O logic that simplifies the implementation of Double Data Rate (DDR) and source synchronous standards. This combination provides support for DDR2 memory interfaces at 400Mbps, high performance ADC/DACs at up to 750Mbps and 7:1 LVDS display interfaces at above 600Mbps. LatticeXP2 devices are available in a number of space saving Chip Scale Ball Grid Array (csBGA) packages, thin as well as standard Fine Pitch Ball Grid Array (ftBGA and fpBGA) packages and popular TQFP and PQFP options.
Samples of the first member of the LatticeXP2 family, the 17K LUT LatticeXP2-17, in 208PQFP, 256ftBGA and 484fpBGA packages are available now. Lattice plans to bring the entire device family to market during 2007. The LatticeXP2-17 will be priced as low as $12.00 in 100,000 unit quantities for delivery in 2008.