Lattice Semiconductor Corporation (NASDAQ: LSCC) has enhanced their LatticeSCM[tm] FPGA family-based SPI4.2 MACO[tm] (“Masked Array for Cost Optimization”) cores by adding sophisticated link layer buffer management options. Compared to competitive FPGAs, the LatticeSCM FPGA family offeres the most feature-rich SPI4.2-based cores and bridge reference designs at the lowest cost, power and printed circuit board footprint. These new features enhance this solution portfolio by allowing designers the option to use a parameterizable buffer manager for applications needing per-channel bandwidth management.
The LatticeSCM FPGA platform provides designers with multiple hardened SPI4.2 cores using Lattice’s exclusive MACO structured ASIC technology. MACO technology delivers pre-engineered, standard-compliant IP functions, developed by Lattice, that shorten end-system time to market and dramatically lower device cost, power and PCB footprint targets. These new features provide designers with a programmable buffer manager capable of:
- Up to 16 separate physical FIFOs per TX/RX direction
- Packet over-flow and error drop
- Both store & forward as well as cut-through operation
- Parameterizable buffer depth and thresholds
- Dynamic channel provisioning
- Programmable sequencer-based scheduler