Lattice Semiconductor Corporation (NASDAQ: LSCC) rolled out Service Pack 2 for their ispLEVER® 7.0 FPGA design tool suite. The new release features additional usability and accuracy enhancements to the Power Calculator, new versions of Synplicity’s Synplify synthesis and Mentor Graphics’ Precision RTL synthesis, and new support for the LatticeMico32(tm) embedded open source microprocessor. Lattice’s Service Pack 2 for ispLEVER 7.0 for Windows, LINUX, and UNIX users is available immediately without charge for customers with active design tool maintenance contracts. The full ispLEVER design tool suite starts at a price of $895 for the Windows version.
This latest release of the LatticeMico32 adds support for multiple bus arbitration schemes, allows VHDL users to implement the LatticeMico32 in their designs, and adds Linux OS-based development tools. The Mico System Builder automatically generates the appropriate Wishbone Bus arbitration scheme when the microprocessor platform is generated for shared-bus or slave-side arbitration to allow multiple master ports access to multiple slave ports.
More info: Lattice Semiconductor