Lattice Semiconductor has released samples of the LatticeECP3-150 low-power ECP3 mid-range FPGA family. Samples have already been shipping to select customers since last month. The ECP3-150 FPGA features a DSP capacity of 320 18×18 multipliers, 6.8 Mbits of memory, and up to sixteen 3.2Gbps SERDES channels. The FPGA is ideal for highly complex and integrated Wireless Remote Radio Heads (RRH) — such as MIMO-based RF antenna solutions. The ECP3-150 FPGA also provides Wireline Access developers with unprecedented high-density, low-cost, low-power Ethernet, SONET and PCI Express solutions, with the lowest cost points and power footprints in the FPGA industry.
LatticeECP3-150 engineering samples are available now in two low-cost wirebond packages (672 fpBGA and 1156 fpBGA). Prices for the LatticeECP3-150 in the 672 fpBGA package in 25K unit volumes start at $75. The LatticeECP3-70 and LatticeECP3-95, which were production released in February, are priced at $35 and $50, respectively, in 25K unit volumes.
The LatticeECP3 FPGA family consists of five devices that offer standards-compliant multi-protocol 3G SERDES, DDR1/2/3 memory interfaces for low cost FPGAs and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O.
LatticeECP3 FPGA Features
- 3.2Gbps SERDES with 10GbE XAUI jitter compliance and the ability to mix and match multiple protocols on each SERDES quad. This includes PCI Express, CPRI, OBSAI, XAUI, Serial RapidIO and SGMII/Gigabit Ethernet.
- The SERDES/PCS blocks have been designed specifically to enable the design of the low latency variation CPRI links that are found in wireless basestations with Remote Radio Head connectivity.
- Compliance to the SMPTE Serial Digital Interface standard, with the unprecedented ability to support 3G, HD and SD video broadcast signals independently on each SERDES channel. The triple rate support is performed without any oversampling technique, consuming the least possible amount of power.
- DSP blocks allowing up to 36×36 Multiply and Accumulate functions running at >400MHz. The DSP slices also feature innovative cascadability for implementing wide ALU and adder tree functions without the performance bottlenecks of FPGA logic.
- 1Gbps LVDS I/O, with Input Delay blocks, allows interfacing to high performance ADCs and DACs.
More information: LatticeECP3 Family