LatticeECP3 65nm FPGA Family

Lattice Semiconductor rolled their 65nm LatticeECP3 FPGA family. The LatticeECP3 features the industry’s lowest power consumption and price of any SERDES-capable FPGA device. The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs. The entire LatticeECP3 family is manufactured using Fujitsu’s advanced low power process technology, and is the only 65nm mid-range, high value FPGA family in the industry. Production devices are available now. In 25K unit volume and the FN484 wirebond package, the LatticeECP3-70 is priced as low as $35 and the LatticeECP3-95 is priced as low as $50.

The LatticeECP3 FPGA family is ideal for deployment in high volume cost- and power-sensitive wireless infrastructure and wireline access equipment, as well as video and imaging, applications.

LatticeECP3 FPGA Features

  • Lowest-Power FPGA with SERDES
    • Low Power 65-nm process
    • Up to 80% lower static power, and 50% lower total power relative to the competition
    • Less than 100mW per SERDES channel @ 3.2 Gbps
  • Optimized FPGA Architecture
    • 4-input look-up table (LUT) fabric
    • Logic densities from 17K to 149K LUTs
    • Upto 6.8Mbits of Embedded Block RAM (EBR)
    • 2 DLLs per device, 2 to 10 PLLs per device
  • Cascadable sysDSP With ALU
    • Multiply, accumulate, addition and subtraction
    • High performance Adder Trees and MMAC functionality
    • 54-bit cascadable arithmetic logic unit
    • 24 to 320 multipliers (18×18)
  • Advanced Configuration Options
    • Parallel burst mode for SPI Flash
    • Automatic multi-boot capability
    • On chip 128 bit AES decryption
    • Live update with TransFR Technology
  • High Speed Embedded SERDES
    • Up to 16 channels @ 3.2Gbps
    • Data rates from 250Mbps to 3.2Gbps
    • IEEE802.3-2002 XAUI Jitter Compliant
    • Mixed Protocol and Mixed Rate support
    • Supports PCI Express, Ethernet (GbE, XAUI, & SGMII), SMPTE, Serial Rapid I/O, CPRI and OBSAI
  • Flexible sysIO Buffers
    • LVCMOS 33/25/18/15/12, PCI, SSTL3/2/18 & HSTL15 & HSTL18
    • 800 Mbps DDR3, 1 Gbps LVDS
  • Wide Range of Package and User I/O Options
    • Up to 586 user I/O pins
    • Low cost wirebond fpBGA packages
    • Pb-free / RoHS-compliant

More info: Lattice Semiconductor