Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the successful interoperation of its LatticeECP2M(tm) FPGA family with the Linear Technology LTC2274, 16-bit, 105Msps, high-speed ADC (Analog to Digital Converter) in support of the JESD204 high-speed serial specification from the JEDEC group. This capability has been demonstrated utilizing standard evaluation boards from both companies.
With devices starting at a price of less than $10.00 in high volume, LatticeECP2M FPGAs provide the lowest cost SERDES-capable FPGAs available, and provide uniquely cost-effective solutions for designs using JESD204/high- speed ADC devices.
Lattice offers a development board that enables customers to quickly develop a JESD204 receiver using the LatticeECP2M SERDES block. The incoming data can then be processed using the LatticeECP2M fabric and high-speed sysDSP(tm) blocks.
A reference design can also be provided to allow interoperation with the LTC2274.
More info: Lattice LatticeECP2M SERDES Evaluation Board