Lattice Serial RapidIO 2.1 Endpoint IP Core Supports 4 x 3.125Gbps

Lattice Semiconductor has extended the Serial RapidIO 2.1, Level 1 endpoint core to support 4 x 3.125Gbps. The previous version of the LatticeECP3 FPGA IP core supported 1x and 2x up to 3.125Gbps and 4x up to 2.5Gbps. The Lattice core can be used with the Lattice Advanced Mezzanine Card (AMC) form factor platform. The Serial RapidIO 2.1 IP core and associated AMC platform are available now for evaluation and use.

Lattice Semiconductor Serial RapidIO 2.1, Level 1 endpoint core

Serial RapidIO 2.1 IP Core Highlights

  • Allows for 1x, 2x and 4x lane configurations
  • Supports up to 3.125Gbps
  • Implements physical layer, transport layer, maintenance transaction handling and RapidIO error management extensions
  • Provides infrastructure support for external logical layer functions, enabling maximum flexibility
  • Provides a choice of how logic layer functions interact with the rest of the system – SoC bus or streaming interfaces
  • Supports software implementations of control plane-oriented functions such as doorbells and messages
  • Compliant with Rev. 2.1 of the specification
  • Backward compatible with the v1.3 specification
  • 64-bit internal data paths
  • Hardware error recovery
  • Integrated buffer module for transmit and receive packet buffering
  • Management Entity with integrated decoder for RapidIO maintenance transactions
  • Management Entity supports optional soft packet interface which enables software implementations of logical layer functions

More info: Lattice Semiconductor