Lattice Semiconductor and Epson Toyocom teamed together on a low-cost reference clock solution for SERDES applications. The reference design features Lattice’s ispClock 5400D device and Epson Toyocom’s SG-710ECK CMOS oscillator. The 6-output ispClock5406D device is available for $2.95 in 10K piece volumes. The Epson Toyocom SG-710 is available for $0.95 in quantities of 10K piece volumes. The reference clock solution is ideal for designers who need a low cost reference clock for SERDES applications such as XAUI or SDI Video.
With the reference clock, SERDES-based designs don’t require an expensive LVDS or LVPECL high frequency oscillator. XAUI, SDI Video and other SERDES applications can now utilize the ultra low-noise, programmable differential output of the Lattice ispClock device, driven by Epson Toyocom’s low-cost CMOS oscillator. This solution is a excellent alternative to traditional, more expensive high frequency differential clock sources.
SERDES (SERializer/DESerializer) applications typically use costly differential interface oscillators with frequencies greater than 150MHz to meet stringent jitter specifications. Lattice’s ispCLOCK5400D device has a low phase noise on-chip PLL that generates these higher clock frequencies. This high frequency is generated by multiplying an Epson Toyocom low-cost, lower frequency CMOS oscillator. The ispCLOCK5400D device accepts the oscillator’s CMOS input. This input is then multiplied up to the appropriate frequency for the SERDES reference clock rate.
The solution is available for popular SERDES reference clock frequencies such as 156.25 MHz, 270 MHz and 312.50 MHz. The programmable output interface of the ispClock5400D device can drive multiple differential interface requirements such as LVDS or LVPECL. For example, with this reference clock the LaticeECP3 FPGA implementing XAUI and SDI Video functions met jitter requirements across the industrial temperature range. ispCLOCK5400D evaluation boards are available for engineers for examining the clock solution.