The low-power LatticeECP3-150 FPGA has been fully qualified and released to volume production by Lattice Semiconductor. LatticeECP3-150 devices are available now in two low-cost wirebond packages (672 fpBGA and 1156 fpBGA). Prices for the LatticeECP3-150 in the 672 fpBGA package in 25K unit volumes start at $75. The LatticeECP3-70 and LatticeECP3-95, which were production released in February, are priced at $35 and $50, respectively, in 25K unit volumes. The LatticeECP3-150 is a member of the ECP3 mid-range FPGA family.
The ECP3-150 device features a DSP capacity of 320 18×18 multipliers, 6.8 Mbits of memory and up to sixteen 3.2Gbps SERDES channels, making it ideal for highly complex and integrated Wireless Remote Radio Heads (RRH) such as MIMO-based RF antenna solutions. The ECP3-150 FPGA also provides Wireline Access developers with unprecedented high-density, low-cost, low-power Ethernet, SONET and PCI Express solutions, with the lowest cost points and power footprints in the FPGA industry.
A range of intellectual property (IP) cores, including Crest Factor Reduction (CFR), Digital Pre-Distortion (DPD), CPRI, OBSAI, Serial RapidIO, XAUI, SGMII/Gigabit Ethernet, PCI Express, SMPTE for serial connectivity, FIR filters, FFT, Reed-Solomon encoders/decoders, CORDIC, CIC, NCO for DSP functions and several others for memory interfaces and connectivity, are available from Lattice Semiconductor and its partners to enable developers to develop time-to-market solutions.
The LatticeECP3 FPGA family consists of five devices that offer standards-compliant multi-protocol 3G SERDES, DDR1/2/3 memory interfaces for low cost FPGAs and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O.
The LatticeECP3 FPGA family is ideal for deployment in high volume cost- and power-sensitive wireless infrastructure and wireline access equipment, as well as video and imaging, applications.
The LatticeECP3 FPGA family is supported by the ispLEVER design tool suite, version 8.0. The ispLEVER design tool suite is the flagship design environment for the latest Lattice FPGA products. It provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, power analysis, place and route, on-chip logic analysis and more. The ispLEVER tool suite is provided on CD-ROM and DVD for Windows, UNIX or Linux platforms. Synopsys’ Synplify Pro advanced FPGA synthesis is included for all operating systems supported, and Aldec’s Active-HDL Lattice Edition simulator is included for Windows. Lattice devices are also supported by Mentor Graphics ModelSim SE and Precision RTL synthesis and the full versions of Synopsys Synplify Pro and Aldec Active-HDL.