Lattice Semiconductor released Service Pack 1 for ispLEVER 8.0 FPGA design tool suite. Service Pack 1 enhances and extends design support of the LatticeECP3 family to enable users to achieve low cost, low power design goals. The SP1 helps engineers with the board-level behavior of their ECP3-150EA based design (such as power and timing) will match what the tools report. In addition, the service pack also increases DSP application performance in the LatticeECP3 devices.
Service Pack 1 Highlights
- Updates the device values to production characterized silicon for the LatticeECP3-150EA device
- Static timing analysis, timing simulation and power calculation will report results that even more accurately reflect the behavior of the actual production device
- PCS/SERDES calibration settings used for the supported IO protocols have been tuned to provide more robust behavior
- HDL generation of generic DDR interfaces from the IPexpress tool has been enhanced to include two additional interfaces, resulting in more design and implementation flexibility
- Choice of pins for generic DDR interfaces
- Synplify Pro synthesis has added several enhancements, allowing higher performance and lower utilization in DSP-centric applications by further exploiting the unique sysDSP Block cascading capability
The ispLEVER 8.0 Service Pack 1 tool suite for Windows, UNIX and Linux users is available immediately without charge for engineers with active design tool maintenance contracts. Pricing for the full ispLEVER design tool suite starts at $1,295 for the Windows version. The ispLEVER FPGA design tool suite provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, place and route, and in-system logic analysis.
More info: Lattice Semiconductor