IP Cores for LatticeXP2 FPGA

Forty-five ispLeverCORE(TM) Intellectual Property (IP) and third-party vendor IP cores are available for Lattice Semiconductor’s (NASDAQ: LSCC) new 90nm embedded FLASH LatticeXP2(TM) FPGA family. Lattice and its ispLeverCORE Connection partners (CAST, ANAGRAM Technologies, DCD, Eureka Technology, and WDC) have already ported a wide range of cores addressing automotive, communications, consumer, embedded, instrumentation, video and wireless applications to the LatticeXP2 architecture.

Lattice-developed ispLeverCORE IP cores for the LatticeXP2 family are supported by the recently released version 7.0 of the ispLEVER(R) design tool suite via Lattice’s IPexpress(TM) flow, included as a standard feature in the ispLEVER software. The cores include:

  • Block Convolutional Encoder
  • Block Viterbi Decoder
  • Cascaded Integrator-Comb (CIC) Filter
  • Color Space Converter
  • Correlator
  • Dynamic Block Reed-Solomon Decoder
  • Dynamic Block Reed-Solomon Encoder
  • DDR Memory Controller
  • DDR2 Memory Controller
  • FFT Generator
  • Interleaver/De-Interleaver
  • Numerically Controlled Oscillator (NCO)
  • PCI Master/Target 32-bit, PCI Master/Target 64-bit, PCI Target 32-bit, PCI Target 64-bit
  • Tri-Speed Ethernet MAC
  • Turbo Encoder

IP cores from Lattice’s ispLeverCORE Connection partners are also supported by version 7.0 of the ispLEVER design tool suite. The following cores are available (listed by vendor):

  • ANAGRAM Technologies – SoftAMP Digital Class-D Controller, SoftDAC 24-bit Audio DAC
  • CAST – CAN Bus Controller, H16550S Synchronous UART with optional FIFO, R8051XC Configurable 8-bit Microcontroller, SDLC Controller, Baseline JPEG Codec, Baseline JPEG Decoder, Baseline JPEG Encoder
  • DCD – Serial Peripheral Interface-Master/Slave, Serial Peripheral Interface-Slave, Serial Peripheral Interface-Master/Slave with FIFO, D16450 Configurable UART, D16550 Configurable UART with FIFO, D16750 Configurable UART with FIFO, DI2CSB I2C Master, DI2CSB I2C Slave, DI2CSB I2C Slave Base Version, DP8051 8-bit Pipelined Microcontroller
  • Eureka Technology – CompactFlash/PCMCIA Host Adapter, NAND Flash Controller, PowerPC Bus Arbiter, PowerPC Bus Master, PowerPC Bus Slave, SD/SDIO Controller
  • WDC – W65C02SRTL 8-bit 65xx Microprocessor, W65C816SRTL 8/16-bit 65xx Microprocessor

Lattice’s ispLeverCORE modules are optimized for use with Lattice devices. The modules are large, modular design blocks, commonly known as intellectual property (IP) cores, which can be reused and easily placed within a programmable logic design. ispLeverCORE IP cores are configured for specific customer applications via the IPexpress module included within the ispLEVER tool. The IPexpress flow allows customers to parameterize IP on their desktop, incorporate the IP within their designs and evaluate the resulting design within their hardware before committing to purchase an IP license. The modules are designed using the highest coding standards and are extensively tested to meet the required functionality and performance. These cores are ready-to-use, well documented and supported by Lattice field and factory engineers.

All Lattice-developed ispLeverCORE IP modules are supported by the IPexpress design flow within ispLEVER version 7.0. Lattice’s comprehensive ispLEVER design software, providing support for all Lattice CPLDs and FPGAs, including IPexpress support, is priced at a low $695 for a complete Windows-based seat. The ispLeverCORE Connection IP cores are available for purchase immediately from the respective ispLeverCORE Connection partners.

More info:
» Lattice Announces IP Cores for 90nm Embedded FLASH LatticeXP2 FPGA
» Lattice IP Cores