Lattice Semiconductor Introduces Tiny iCE40 LP384 FPGA

Lattice Semiconductor iCE40 LP384 FPGA

Lattice Semiconductor announced the iCE40 LP384 FPGA. It is the smallest member of the iCE40 family of ultra-low density FPGAs. The iCE40 LP384 FPGA architecture is ideal for capturing and processing large amounts of data at hardware speeds while using very little power and board space. The iCE40 LP384 FPGA devices are available in sample quantities. Present packaging options include 32-pin QFNs (5.0 mm x 5.0 mm), 36-ball ucBGAs (2.5 mm x 2.5 mm), and 49-pin ucBGAs (3.0 mm x 3.0 mm).

Lattice Semiconductor iCE40 LP384 ultra-low density FPGAs

The Lattice iCE40 LP384 FPGA includes the programmable logic, flexible IO, and on-chip memory necessary to process data at speeds greater than ASSPs or companion microprocessors while simultaneously reducing power consumption for an equivalent cost. Lattice Semiconductor also includes reference designs and application notes to accelerate development and reduce time-to-market by several months.

The iCE40 LP384 is a tiny, low power, low cost FPGA. It has a capacity of 384 LUTs, and consumes 25-Microwatts static core power. The Lattice device comes in packages as small as 2.5 mm x 2.5 mm with a migration path to 2.0 mm x 2.0 mm and costs less than 50 cents per unit in multi-million unit quantities.

The iCE40 LP384 FPGA helps designers to rapidly add new features and differentiate cost-sensitive, space-constrained, low-power product. The new small footprint FPGA is ideal for portable medical monitors, smartphones, digital cameras, eReaders, and compact embedded systems.

Lattice Semiconductor iCE40 LP384 FPGA Features

  • Four devices with 384 to 7,680 LUT4s and 21 to 206 I/Os
  • Advanced 40 nm low power process
  • As low as 25 µW standby power
  • Programmable low swing differential I/Os
  • Up to 128 Kbits sysMEM Embedded Block RAM
  • DDR registers in I/O cells
  • Programmable sysIO buffer supports wide range of interfaces:
    • LVCMOS 3.3/2.5/1.8
    • LVDS25E, subLVDS
    • Schmitt trigger inputs, to 200 mV typical hysteresis
  • Programmable pull-up mode
  • Eight low-skew global clock resources
  • Up to two analog PLLs per device
  • SRAM is configured through:
    • Standard SPI Interface
    • Internal Nonvolatile Configuration Memory (NVCM)
  • QFN, VQFP, TQFP, ucBGA, caBGA, and csBGA package options
  • Small footprint package options — as small as 2.5×2.5mm
  • Advanced halogen-free packaging

More info: Lattice Semiconductor iCE40 LP/HX FPGA Family (pdf)