Lattice Semiconductor (NASDAQ: LSCC) recently announced HyperTransport(TM) support and the release of the PURESPEED I/O Alignment Reference Design.
The LatticeSC(TM) and LatticeSCM(TM) FPGA families (LatticeSC/M families) now support HyperTransport technology at rates up to 1600Mbps, QDRII+ rates up to 750Mbps, RLDRAM(R) II rates of 800Mbps and DDR2 interface speeds of 667Mbps. HyperTransport technology and the memory interfaces are implemented using the LatticeSC/M families’ innovative PURESPEED(TM) I/O technology. The memory controller IP (intellectual property) is implemented in Lattice’s unique and low power Masked Array for Cost Optimization (MACO(TM)) structured ASIC technology.
Lattice’s unique MACO embedded structured ASIC blocks are available on LatticeSCM FPGA devices and deliver pre-engineered, standard-compliant IP functions developed by Lattice to shorten end-system time to market. The enhanced DDR, RLDRAM and QDR memory controllers also are available on the LatticeSC/M family of FPGAs, and are supported by Lattice’s next generation of design tools, the recently announced ispLEVER(R) version 7.0 software design tool suite. There is no IP fee associated with the use of any pre-engineered, MACO-based IP core.
Lattice also released the PURESPEED I/O Alignment Reference Design. This reference design demonstrates the power of the LatticeSC/M families’ patented Adaptive Input Logic block that delivers data rates of up to 2 Gigabits per second. AIL is designed to continuously monitor and dynamically adjust the clock/data relationship on a bit by bit basis with a resolution down to 40 picoseconds. This ability is critical for customers who want to build large, high-speed data pipes out of multiple smaller ones. In the reference design, data is sent across mismatched trace lengths to introduce different amounts of skew. A word alignment block, together with AIL, is used to realign this skewed data bus. This powerful realignment capability is readily observed on an oscilloscope as part of the reference design.