Lattice Diamond Design Software v1.4

Lattice Semiconductor introduced version 1.4 of the Lattice Diamond design software. Lattice Diamond v1.4 features several usability enhancements that make FPGA design exploration easier and reduce time to market. Lattice Diamond v1.4 software is available now for for both Windows and Linux. Once downloaded and installed, the software can be used with either the Lattice Diamond free license or the Lattice Diamond subscription license. The Lattice Diamond free license provides no cost access to many Lattice devices such as the MachXO2 and MachXO device families, the LatticeXP2 and LatticeECP2 FPGA families, and the Platform Manager devices. The Lattice Diamond free license enables Synopsys Synplify Pro for Lattice synthesis as well as the Aldec Lattice Edition II mixed language simulator.

Lattice Diamond v1.4 offers enhanced support for the MachXO2 PLD family. It does this by providing final production timing, power models and bitstreams for the entire family, including the latest wafer-level chip scale packaged version of the LCMXO2-2000U and LCMXO2-1200U devices. In addition, engineers can use Lattice Diamond 1.4 to design with the newly announced low cost, low power mid-range LatticeECP4 FPGA family.

Lattice Diamond v1.4 Highlights

    Final Data Support for the MachXO2 PLD Family
    Includes final data for timing, power, package and bitstream based on the actual silicon characterization of all the MachXO2 devices. The final simultaneous switching output (SSO) data is available for all packages (except the wafer-level chip scale package of the LCMXO2-2000U, which will be made available later). Engineers can now design and analyze using the most current data when targeting MachXO2 devices.

    Early Access to the New LatticeECP4 FPGA Family
    Select customers will be able to use Lattice Diamond 1.4 software to design with these new devices. Lattice Diamond 1.4 provides a complete set of powerful tools specifically targeted to the LatticeECP4 family’s unique logic fabric and its built-in hardened IP blocks to enable lower cost and lower power applications. In particular, a new System Planner tool aids optimizing resource usage, and multiple improvements have been made to the generation of DSP blocks.

    Design Exploration Improves Time to Market
    Provides a report of device resources used by level of design hierarchy following either the synthesis or the map step (a process that maps the synthesis output to the device resources). Device resources can therefore be reported out as both logical (registers) and physical (slices) elements. This feature helps designers quickly understand what parts of the design are using scarce device resources so that they can optimize the design for the targeted device. This information can be exported to a text or a CSV file to enable analysis in other tools.

    Improved Ease of Use
    The pin assignment Design Rule Check (DRC) engine has been redesigned and implemented for the LatticeECP3, MachXO2 and LatticeSC device families to provide real-time as well as on-demand DRC during pin assignment and configuration, and a user-friendly report that helps identify and correct pin usage issues. In addition, users of the Lattice Synthesis Engine (LSE) tool can now create and edit Synopsys Design Compiler (SDC) synthesis constraints in the new Lattice Design Constraints graphical editor. This editor automatically populates design clock, port and net names and provides real time syntax and semantic checks. It generates an SDC file that can be used with LSE.

More info: Lattice Semiconductor