Avnet Lattice High Speed Interface SpeedWay Design Workshops

Avnet Electronics Marketing, a division of Avnet, Inc. (NYSE: AVT), and Lattice Semiconductor (NASDAQ: LSCC) are offering workshops that feature high-speed interfaces for Lattice’s FPGAs. Designers, developers and engineers interested in leveraging the latest high-speed interface technologies with FPGAs can get hands-on experience by attending the Avnet Lattice High Speed Interface SpeedWay Design Workshops. The events are scheduled to begin September 18, 2007, in locations throughout the U.S. and in Canada.

Avnet’s factory-trained field applications engineers (FAEs) have developed materials for the full day SpeedWay Workshops with support from Lattice’s applications engineers. Based on practical experience and the latest technologies that highlight proven design techniques, attendees will leave the workshops armed with design knowledge and information that can be applied immediately to current projects.

Workshop agenda:

  • SERDES 101
  • Labs – ispLever Introduction, ipExpress Introduction, SERDES IP and SERDES Demonstration
  • PCI-e Architecture
  • PCI-e Design Considerations
  • Lab – PCI-e IP and PCI-e Demonstration
  • DDR2 Design Considerations
  • Lab – DDR2 IP and DDR2 Demonstration

Workshop attendees will also receive an ECP2 Advanced Evaluation Board (a $2400 value) with their $149 paid registration.

More info:
Avnet SpeedWay Design Workshops Feature Lattice FPGAs
Avnet Lattice High Speed Interface SpeedWay Design Workshops
Lattice Semiconductor