Lattice Semiconductor introduced version six of their PAC-Designer design software. Lattice PAC-Designer enables analog and board designers to integrate a circuit board’s power management and digital board management functions into the newly announced Platform Manager device family. PAC-Designer 6.0 features a simple, easy to learn, push-button design methodology. The tool enables engineers to implement designs into the FPGA portion of the Platform Manager devices. PAC-Designer software and companion ispLEVER Starter for Windows can be downloaded now for free.
Lattice PAC-Designer 6.0 Highlights
- GUI-based design methodology for analog engineers using intuitive dialog boxes to configure analog sections
- LogiBuilder design methodology to integrate power management functions into the on-chip CPLD
- LogiBuilder or VHDL or Verilog design methodology to integrate digital board management functions into the FPGA section of the Platform Manager devices
- Provides three free correct-by-construction IP cores to implement functions such as closed-loop margining with Voltage ID (VID) Support, I2C/SPI slave interface and non-volatile fault logging into external SPI memory
- Digital designers can also use ispLEVER 8.1 software to integrate other board management functions into the on-chip FPGA section using standard digital design methods
More information: Lattice Semiconductor