Lattice ispLEVER FPGA Design Tool 7.0

Lattice Semiconductor Corporation (NASDAQ: LSCC) announced major performance and functional enhancements in Version 7.0 of its ispLEVER(R) FPGA design tools. Optimized logic synthesis, map, and place-and-route algorithms have boosted Lattice FPGA performance demonstrably by 12% on average, with certain large, system-level benchmark circuits benefiting by an over 40% improvement, compared to the previous ispLEVER release.

Tool performance has also been substantially improved, dramatically reducing design fit runtime and workstation memory requirements. In addition, the ispLEVER 7.0 software features Reveal(TM), Lattice’s second generation logic analysis / hardware debug tool, a more accurate and user friendly Power Calculator module and a variety of enhancements to the LatticeMico32(TM) embedded open source microprocessor design tools. Full support for the newly announced LatticeXP2(TM) 90nm non-volatile FPGA device family has been added to Lattice’s ever growing portfolio of supported architectures.

FPGA performance has increased by up to 46% for system-level FPGA benchmark designs requiring >50K LUTs, averaging 12% across a wide range of typical design benchmarks and densities of Lattice FPGAs. In addition, for large FPGA designs where runtime is most critical, Lattice’s ispLEVER 7.0 software has reduced design compile times by more than 70%, with an average improvement of approximately 30% faster. Finally, the amount of workstation RAM required to successfully complete large, densely packed designs has also been reduced by almost 40%, allowing PC-based design fitting for larger LatticeSC(TM) FPGA designs.

Major new features include:

  • Designed to support the FPGA designer’s intuitive design debug process, the Reveal logic analyzer uses a signal-centric model for embedded logic debug.
  • The ispLEVER Power Calculator has been enhanced with a new environment-aware power model, new graphical power displays and a variety of useful reports.
  • LatticeMico32 soft microprocessor system design, now supporting the LatticeXP2 family, includes new features as well.

Lattice’s ispLEVER 7.0 for Windows, LINUX and UNIX users is available immediately starting at a price of $895 for the Windows PC version. The annual, node-locked license for ispLEVER PRO, supporting an unlimited number of IP-based FPGA designs, carries an attractive $1495 list price.

More info:
» Lattice Improves ispLEVER FPGA Design Tools by 12%
» ispLEVER
» Lattice Semiconductor